encode circuit中文
編碼電路
例句與用法
- The chapter of hardware design first expounds the whole design . the several primary circuit are designed , including power circuit , controlling circuit , detecting circuit and the dsp quadrature encode circuit
硬件部分先作了整體設計的論述,然后具體介紹了功率電路、控制電路、檢測電路以及dsp的正交解碼電路。 - As the random structure of ldpc codes made it difficult to encoding in hardware and few mathematic methods has been found for analyzing these codes , many constructed ldpc codes were investigated to simplify encoding circuit and to reduce the complexity of analyses
隨機構造的ldpc碼缺乏系統的分析理論,且編碼部分的硬件實現困難,成為ldpc碼應用的一個瓶頸,因此許多的結構化的ldpc碼被相繼提出,以簡化編碼的硬件復雜度和理論分析的難度。 - Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc , according to the system performance , the specifications of sub _ adc is obtained , while the sub _ adc including the preamplifier - latch comparator , the reference ladder resistance and the clock - control encode circuits are discussed in detail
基于對10 - bit100mspspipelinedcmosadc系統結構的分析研究,結合系統性能確定了子adc的指標要求,詳細討論并設計了子adc單元模塊的設計,包括預放大鎖存比較器,參考電阻串和時鐘控制編碼電路。 - Secondly , compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory , a novel topology of cmos preamplifier latch comparator circuit is presented . considering trade - off between kickback noise and power dissipation , reference resistance value is optimized . according to the encode demands of different stage resolution , clock - control encode circuit is designed
其后,在具體的子adc設計中,對比各比較器類型的優缺點,并基于預放大鎖存快速比較理論,提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制,在回饋噪聲對輸入參考電平的影響和功耗之間折衷,確定優化的參考電阻串阻值;根據不同級精度的編碼要求,設計出時鐘控制編碼電路。